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na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 xx555 precision timers 1 features 3 description these devices are precision timing circuits capable of 1 ? timing from microseconds to hours producing accurate time delays or oscillation. in the ? astable or monostable operation time-delay or mono-stable mode of operation, the ? adjustable duty cycle timed interval is controlled by a single external resistor and capacitor network. in the a-stable mode ? ttl-compatible output can sink or source of operation, the frequency and duty cycle can be up to 200 ma controlled independently with two external resistors ? on products compliant to mil-prf-38535, and a single external capacitor. all parameters are tested unless otherwise the threshold and trigger levels normally are two- noted. on all other products, production thirds and one-third, respectively, of v cc . these processing does not necessarily include levels can be altered by use of the control-voltage testing of all parameters. terminal. when the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. if 2 applications the trigger input is above the trigger level and the ? fingerprint biometrics threshold input is above the threshold level, the flip- flop is reset and the output is low. the reset (reset) ? iris biometrics input can override all other inputs and can be used to ? rfid reader initiate a new timing cycle. when reset goes low, the flip-flop is reset, and the output goes low. when the output is low, a low-impedance path is provided between discharge (disch) and ground. the output circuit is capable of sinking or sourcing current up to 200 ma. operation is specified for supplies of 5 v to 15 v. with a 5-v supply, output levels are compatible with ttl inputs. device information (1) part number package body size (nom) pdip (8) 9.81 mm 6.35 mm sop (8) 6.20 mm 5.30 mm xx555 tssop (8) 3.00 mm 4.40 mm soic (8) 4.90 mm 3.91 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. 4 simplified schematic 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder 1 s r r1 trig thres v cc cont reset outdisch gnd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 8 5 62 1 7 3 support &community tools & software technical documents sample &buy
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com table of contents 8.1 overview ................................................................... 9 1 features .................................................................. 1 8.2 functional block diagram ......................................... 9 2 applications ........................................................... 1 8.3 feature description ................................................... 9 3 description ............................................................. 1 8.4 device functional modes ........................................ 12 4 simplified schematic ............................................. 1 9 applications and implementation ...................... 13 5 revision history ..................................................... 2 9.1 application information ............................................ 13 6 pin configuration and functions ......................... 3 9.2 typical applications ................................................ 13 7 specifications ......................................................... 4 10 power supply recommendations ..................... 18 7.1 absolute maximum ratings ..................................... 4 11 device and documentation support ................. 19 7.2 handling ratings ....................................................... 4 11.1 related links ........................................................ 19 7.3 recommended operating conditions ....................... 4 11.2 trademarks ........................................................... 19 7.4 electrical characteristics ........................................... 5 11.3 electrostatic discharge caution ............................ 19 7.5 operating characteristics .......................................... 6 11.4 glossary ................................................................ 19 7.6 typical characteristics .............................................. 7 12 mechanical, packaging, and orderable 8 detailed description .............................................. 9 information ........................................................... 19 5 revision history changes from revision h (june 2010) to revision i page ? updated document to new ti enhanced data sheet format. .................................................................................................. 1 ? deleted ordering information table. ...................................................................................................................................... 1 ? added military disclaimer to features list. ............................................................................................................................. 1 ? added applications. ................................................................................................................................................................ 1 ? added device information table. ............................................................................................................................................ 1 ? moved t stg to handling ratings table. .................................................................................................................................... 4 ? added disch switch on-state voltage parameter. ................................................................................................................. 5 ? added device and documentation support section. ............................................................................................................ 19 ? added esd warning. ............................................................................................................................................................ 19 ? added mechanical, packaging, and orderable information section. .................................................................................... 19 2 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 6 pin configuration and functions pin functions pin d, p, ps, fk i/o description pw, jg name no. controls comparator thresholds, outputs 2/3 vcc, allows bypass capacitor cont 5 12 i/o connection disch 7 17 o open collector output to discharge timing capacitor gnd 1 2 ? ground 1, 3, 4, 6, 8, 9, 11, 13, nc ? no internal connection 14, 16, 18, 19 out 3 7 o high current timer output signal reset 4 10 i active low reset input forces output and discharge low. thres 6 15 i end of timing input. thres > cont sets output low and discharge low trig 2 5 i start of timing input. trig < ? cont sets output high and discharge open v cc 8 20 ? input supply voltage, 4.5 v to 16 v. (se555 maximum is 18 v) copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: na555 NE555 sa555 se555 12 3 4 87 6 5 gnd trig out reset v cc dischthres cont 3 2 1 20 19 9 10 11 12 13 45 6 7 8 1817 16 15 14 ncdisch nc thres nc nc trig nc out nc ncgnd nc cont nc v cc nc nc reset nc nc C no internal connection na555...d or p package NE555...d, p, ps, or pw package sa555...d or p package se555...d, jg, or p package (top view) se555...fk package (top view)
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com 7 specifications 7.1 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage (2) 18 v v i input voltage cont, reset, thres, trig v cc v i o output current 225 ma d package 97 p package 85 ja package thermal impedance (3) (4) c/w ps package 95 pw package 149 fk package 5.61 jc package thermal impedance (5) (6) c/w jg package 14.5 t j operating virtual junction temperature 150 c case temperature for 60 s fk package 260 c lead temperature 1,6 mm (1/16 in) from case for 60 s jg package 300 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to gnd. (3) maximum power dissipation is a function of t j (max), ja , and t a . the maximum allowable power dissipation at any allowable ambient temperature is p d = (t j (max) - t a ) / ja. operating at the absolute maximum t j of 150 c can affect reliability. (4) the package thermal impedance is calculated in accordance with jesd 51-7. (5) maximum power dissipation is a function of t j (max), jc , and t c . the maximum allowable power dissipation at any allowable case temperature is p d = (t j (max) - t c ) / jc . operating at the absolute maximum t j of 150 c can affect reliability. (6) the package thermal impedance is calculated in accordance with mil-std-883. 7.2 handling ratings parameter definition min max unit t stg storage temperature range ? 65 150 c 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit na555, NE555, sa555 4.5 16 v cc supply voltage v se555 4.5 18 v i input voltage cont, reset, thres, and trig v cc v i o output current 200 ma na555 ? 40 105 NE555 0 70 t a operating free-air temperature c sa555 ? 40 85 se555 ? 55 125 4 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 7.4 electrical characteristics v cc = 5 v to 15 v, t a = 25 c (unless otherwise noted) na555 se555 NE555 parameter test conditions unit sa555 min typ max min typ max v cc = 15 v 9.4 10 10.6 8.8 10 11.2 thres voltage level v v cc = 5 v 2.7 3.3 4 2.4 3.3 4.2 thres current (1) 30 250 30 250 na 4.8 5 5.2 4.5 5 5.6 v cc = 15 v t a = ? 55 c to 125 c 3 6 trig voltage level v 1.45 1.67 1.9 1.1 1.67 2.2 v cc = 5 v t a = ? 55 c to 125 c 1.9 trig current trig at 0 v 0.5 0.9 0.5 2 a 0.3 0.7 1 0.3 0.7 1 reset voltage level v t a = ? 55 c to 125 c 1.1 reset at v cc 0.1 0.4 0.1 0.4 reset current ma reset at 0 v ? 0.4 ? 1 ? 0.4 ? 1.5 disch switch off-state 20 100 20 100 na current disch switch on-state v cc = 5 v, i o = 8 ma 0.15 0.4 v voltage 9.6 10 10.4 9 10 11 v cc = 15 v t a = ? 55 c to 125 c 9.6 10.4 cont voltage v (open circuit) 2.9 3.3 3.8 2.6 3.3 4 v cc = 5 v t a = ? 55 c to 125 c 2.9 3.8 0.1 0.15 0.1 0.25 v cc = 15 v, i ol = 10 ma t a = ? 55 c to 125 c 0.2 0.4 0.5 0.4 0.75 v cc = 15 v, i ol = 50 ma t a = ? 55 c to 125 c 1 2 2.2 2 2.5 v cc = 15 v, i ol = 100 ma low-level output voltage t a = ? 55 c to 125 c 2.7 v v cc = 15 v, i ol = 200 ma 2.5 2.5 v cc = 5 v, i ol = 3.5 ma t a = ? 55 c to 125 c 0.35 0.1 0.2 0.1 0.35 v cc = 5 v, i ol = 5 ma t a = ? 55 c to 125 c 0.8 v cc = 5 v, i ol = 8 ma 0.15 0.25 0.15 0.4 13 13.3 12.75 13.3 v cc = 15 v, i oh = ? 100 ma t a = ? 55 c to 125 c 12 high-level output voltage v cc = 15 v, i oh = ? 200 ma 12.5 12.5 v 3 3.3 2.75 3.3 v cc = 5 v, i oh = ? 100 ma t a = ? 55 c to 125 c 2 v cc = 15 v 10 12 10 15 output low, no load v cc = 5 v 3 5 3 6 supply current ma v cc = 15 v 9 10 9 13 output high, no load v cc = 5 v 2 4 2 5 (1) this parameter influences the maximum value of the timing resistors r a and r b in the circuit of figure 12 . for example, when v cc = 5 v, the maximum value is r = r a + r b ? 3.4 m ? , and for v cc = 15 v, the maximum value is 10 m ? . copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: na555 NE555 sa555 se555
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com 7.5 operating characteristics v cc = 5 v to 15 v, t a = 25 c (unless otherwise noted) na555 se555 NE555 test parameter unit sa555 conditions (1) min typ max min typ max each timer, monostable (3) t a = 25 c 0.5 1.5 (4) 1 3 initial error of timing % interval (2) each timer, astable (5) 1.5 2.25 each timer, monostable (3) t a = min to max 30 100 (4) 50 temperature coefficient of ppm/ timing interval c each timer, astable (5) 90 150 each timer, monostable (3) t a = 25 c 0.05 0.2 (4) 0.1 0.5 supply-voltage sensitivity of %/v timing interval each timer, astable (5) 0.15 0.3 c l = 15 pf, output-pulse rise time 100 200 (4) 100 300 ns t a = 25 c c l = 15 pf, output-pulse fall time 100 200 (4) 100 300 ns t a = 25 c (1) for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. (2) timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) values specified are for a device in a monostable circuit similar to figure 9 , with the following component values: r a = 2 k ? to 100 k ? , c = 0.1 f. (4) on products compliant to mil-prf-38535, this parameter is not production tested. (5) values specified are for a device in an astable circuit similar to figure 12 , with the following component values: r a = 1 k ? to 100 k ? , c = 0.1 f. 6 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 7.6 typical characteristics data for temperatures below ? 40 c and above 105 c are applicable for se555 circuits only. figure 1. low-level output voltage figure 2. low-level output voltage vs low-level output current vs low-level output current figure 3. low-level output voltage figure 4. drop between supply voltage and output vs low-level output current vs high-level output current figure 5. supply current figure 6. normalized output pulse duration vs supply voltage (monostable operation) vs supply voltage copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: na555 NE555 sa555 se555 v cc = 10 v ? low-level output v oltage ? v v ol i ol ? low-level output current ? ma 0.1 0.040.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 t a = 125 c t a = 25 c t a = ?55 c 1 0.60.2 0 1.4 1.8 2.00.4 1.60.8 1.2 ? i oh ? high-level output current ? ma t a = 125 c t a = 25 c 100 70 40 20 10 7 4 2 1 v cc = 5 v to 15 v t a = ?55 c v cc v oh ? v oltage drop ? v ) ( t a = 125 c t a = 25 c i ol ? low-level output current ? ma v cc = 5 v t a = ?55 c 0.1 0.040.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 ? low-level output v oltage ? v v ol 54 2 1 0 9 3 5 6 7 8 9 10 11 ? supply current ? ma 76 8 10 12 13 14 15 t a = 25 c t a = 125 c t a = ?55 c output low, no load cc i v cc ? supply voltage ? v t a = 125 c t a = 25 c t a = ?55 c v cc = 15 v ? low-level output v oltage ? v v ol i ol ? low-level output current ? ma 0.1 0.040.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 1 0.9950.990 0.985 0 5 10 1.005 1.010 1.015 15 20 cc v pulse duration relative to v alue at = 10 v v cc ? supply voltage ? v 8
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com typical characteristics (continued) data for temperatures below ? 40 c and above 105 c are applicable for se555 circuits only. figure 7. normalized output pulse duration figure 8. propagation delay time (monostable operation) vs vs lowest voltage level of trigger pulse free-air temperature 8 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 1 0.9950.990 0.985 ?75 ?25 25 1.005 1.010 1.015 75 125 t a ? free-air temperature ? c ?50 0 50 100 v cc = 10 v pulse duration relative to v alue at t a = 25 c 8 0 100 200 300 400 500 600 700 800 900 1000 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 lowest level of trigger pulse C v cc t pd C propagation delay time C ns t a = 125 c t a = 70 c t a = 25 c t a = 0 c t a = C55 c 8
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 8 detailed description 8.1 overview the xx555 timer is a popular and easy to use for general purpose timing applications from 10 s to hours or from < 1mhz to 100 khz. in the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. in the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. maximum output sink and discharge sink current is greater for higher vcc and less for lower vcc. 8.2 functional block diagram a. pin numbers shown are for the d, jg, p, ps, and pw packages. b. reset can override trig, which can override thres. 8.3 feature description 8.3.1 mono-stable operation for mono-stable operation, any of these timers can be connected as shown in figure 9 . if the output is low, application of a negative-going pulse to the trigger (trig) sets the flip-flop ( q goes low), drives the output high, and turns off q1. capacitor c then is charged through r a until the voltage across the capacitor reaches the threshold voltage of the threshold (thres) input. if trig has returned to a high level, the output of the threshold comparator resets the flip-flop ( q goes high), drives the output low, and discharges c through q1. copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: na555 NE555 sa555 se555 1 s r r1 trig thres v cc cont reset outdisch gnd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 8 5 62 1 7 3
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com feature description (continued) figure 9. circuit for monostable operation monostable operation is initiated when trig voltage falls below the trigger threshold. once initiated, the sequence ends only if trig is high for at least 10 s before the end of the timing interval. when the trigger is grounded, the comparator storage time can be as long as 10 s, which limits the minimum monostable pulse width to 10 s. because of the threshold level and saturation voltage of q1, the output pulse duration is approximately t w = 1.1r a c. figure 11 is a plot of the time constant for various values of r a and c. the threshold levels and charge rates both are directly proportional to the supply voltage, v cc . the timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. applying a negative-going trigger pulse simultaneously to reset and trig during the timing interval discharges c and reinitiates the cycle, commencing on the positive edge of the reset pulse. the output is held low as long as the reset pulse is low. to prevent false triggering, when reset is not used, it should be connected to v cc . figure 10. typical monostable waveforms figure 11. output pulse duration vs capacitance 10 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 v oltage ? 2 v/div t ime ? 0.1 ms/div ?????? ?????? ?????? ?????? capacitor v oltage output v oltage input v oltage ????? ????? ????? ????? ????? r a = 9.1 k w c l = 0.01 m f r l = 1 k w see figure 9 v cc (5 v to 15 v) r a r l output gnd out v cc cont resetdisch thres trig input ? ? ? 5 8 47 6 2 3 1 pin numbers shown are for the d, jg, p , ps, and pw packages. ? output pulse duration ? s c ? capacitance ? m f 10 1 10 ?1 10 ?2 10 ?3 10 ?4 100 10 1 0.1 0.01 10 ?5 0.001 t w r a = 10 m w r a = 10 k w r a = 1 k w r a = 100 k w r a = 1 m w
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 feature description (continued) 8.3.2 a-stable operation as shown in figure 12 , adding a second resistor, r b , to the circuit of figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multi-vibrator. the capacitor c charges through r a and r b and then discharges through r b only. therefore, the duty cycle is controlled by the values of r a and r b . this astable connection results in capacitor c charging and discharging between the threshold-voltage level ( 0.67 v cc ) and the trigger-voltage level ( 0.33 v cc ). as in the mono-stable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. figure 12. circuit for astable operation figure 13. typical astable waveforms figure 12 shows typical waveforms generated during astable operation. the output high-level duration t h and low-level duration t l can be calculated as follows: (1) (2) other useful relationships are shown below: (3) (4) (5) (6) (7) copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: na555 NE555 sa555 se555 v oltage ? 1 v/div t ime ? 0.5 ms/div t h capacitor v oltage output v oltage t l ?????????? ?????????? ?????????? ?????????? r a = 5 k r l = 1 k r b = 3 k see figure 12 c = 0.15 m f ( ) h l a b period t t 0.693 r 2r c = + = + l b h l a b t r output driver duty cycle t t r 2r = = + + ( ) a b 1.44 frequency r 2r c ? + h b h l a b t r output waveform duty cycle 1 t t r 2r = = - + + ( ) h a b t 0.693 r r c = + l b h a b t r low-to-high ratio t r r = = + ( ) l b t 0.693 r c = gnd out v cc cont resetdisch thres trig c r b r a output r l 0.01 m f v cc (5 v to 15 v) (see note a) ? ? ? note a: decoupling cont voltage to ground with a capacitor can improve operation. this should be evaluated for individual applications. open 5 8 47 6 2 3 1 pin numbers shown are for the d, jg, p , ps, and pw packages.
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com feature description (continued) figure 14. free-running frequency 8.3.3 frequency divider by adjusting the length of the timing cycle, the basic circuit of figure 9 can be made to operate as a frequency divider. figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during the timing cycle. figure 15. divide-by-three circuit waveforms 8.4 device functional modes table 1. function table reset trigger voltage (1) threshold voltage (1) output discharge switch low irrelevant irrelevant low on high < 1/3 v cc irrelevant high off high > 1/3 v cc > 2/3 v cc low on high > 1/3 v cc < 2/3 v cc as previously established (1) voltage levels shown are nominal. 12 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 v oltage ? 2 v/div t ime ? 0.1 ms/div capacitor v oltage output v oltage input v oltage ????? ????? ????? ????? ????? v cc = 5 v r a = 1250 w c = 0.02 m f see figure 9 f ? free-running frequency ? hz c ? capacitance ? m f 100 k 10 k 1 k 100 10 1 100 10 1 0.1 0.01 0.1 0.001 r a + 2 r b = 10 m w r a + 2 r b = 1 m w r a + 2 r b = 100 k w r a + 2 r b = 10 k w r a + 2 r b = 1 k w
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 9 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay or operating frequency. this section presents a simplified discussion of the design process. 9.2 typical applications 9.2.1 missing-pulse detector the circuit shown in figure 16 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. the timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. a longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in figure 17 . figure 16. circuit for missing-pulse detector 9.2.1.1 design requirements input fault (missing pulses) must be input high. input stuck low will not be detected because timing capacitor "c" will remain discharged. 9.2.1.2 detailed design procedure choose r a and c so that r a c > [maximum normal input high time]. r l improves v oh , but it is not required for ttl compatibility. copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: na555 NE555 sa555 se555 v cc (5 v to 15 v) disch out v cc reset r l r a a5t3644 c thres gnd cont trig input 0.01 m f ??? ??? ??? ??? output 4 8 37 6 2 5 1 pin numbers shown are shown for the d, jg, p , ps, and pw packages.
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com typical applications (continued) 9.2.1.3 application curves figure 17. completed timing waveforms for missing-pulse detector 9.2.2 pulse-width modulation the operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to cont. figure 18 shows a circuit for pulse-width modulation. a continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. figure 19 shows the resulting output pulse-width modulation. while a sine-wave modulation signal is shown, any wave shape could be used. figure 18. circuit for pulse-width modulation 14 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 thres gnd c r a r l v cc (5 v to 15 v) output disch out v cc reset trigcont modulation input (see note a) clock input note a: the modulating signal can be direct or capacitively coupledto cont . for direct coupling, the ef fects of modulation source voltage and impedance on the bias of the timer should be considered. 4 8 3 76 2 5 pin numbers shown are for the d, jg, p , ps, and pw packages. 1 t ime ? 0.1 ms/div v oltage ? 2 v/div ????? ????? ????? ????? ????? ????? v cc = 5 v r a = 1 k w c = 0.1 m f see figure 15 capacitor v oltage ????? ????? ????? output v oltage input v oltage
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 typical applications (continued) 9.2.2.1 design requirements clock input must have v ol and v oh levels that are less than and greater than 1/3 vcc. modulation input can vary from ground to vcc. the application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is based rc on an negative exponential curve. 9.2.2.2 detailed design procedure choose r a and c so that r a c = 1/4 [clock input period]. r l improves v oh , but it is not required for ttl compatibility. 9.2.2.3 application curves figure 19. pulse-width-modulation waveforms 9.2.3 pulse-position modulation as shown in figure 20 , any of these timers can be used as a pulse-position modulator. this application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: na555 NE555 sa555 se555 v oltage ? 2 v/div t ime ? 0.5 ms/div ?????? ?????? ?????? capacitor v oltage ????? ????? ????? ????? output v oltage ?????? ?????? ?????? ?????? clock input v oltage ????? ????? ????? ????? ????? ????? r a = 3 k w c = 0.02 m f r l = 1 k w see figure 18 ??????? ??????? ??????? modulation input v oltage
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com typical applications (continued) figure 20. circuit for pulse-position modulation 9.2.3.1 design requirements both dc and ac coupled modulation input will change the upper and lower voltage thresholds for the timing capacitor. both frequency and duty cycle will vary with the modulation voltage. 9.2.3.2 detailed design procedure the nominal output frequency and duty cycle can be determined using formulas in a-stable operation section. r l improves v oh , but it is not required for ttl compatibility. 16 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 r b modulation input (see note a) cont trig reset v cc out disch v cc (5 v to 15 v) r l r a c gnd thres note a: the modulating signal can be direct or capacitively coupled to cont . for direct coupling, the ef fects of modulation source voltage and impedance on the bias of the timershould be considered. pin numbers shown are for the d, jg, p , ps, and pw packages. 4 8 3 76 2 5 output
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 typical applications (continued) 9.2.3.3 application curves figure 21. pulse-position-modulation waveforms 9.2.4 sequential timer many applications, such as computers, require signals for initializing conditions during start-up. other applications, such as test equipment, require activation of test signals in sequence. these timing circuits can be connected to provide such sequential control. the timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. figure 22 shows a sequencer circuit with possible applications in many systems, and figure 23 shows the output waveforms. figure 22. sequential timer circuit copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: na555 NE555 sa555 se555 v oltage ? 2 v/div ????? ????? ????? ????? ????? r a = 3 k w r b = 500 w r l = 1 k w see figure 20 ?????? ?????? ?????? ?????? capacitor v oltage ????? ????? ????? ????? output v oltage ??????? ??????? ??????? ??????? modulation input v oltage t ime ? 0.1 ms/div s v cc reset v cc out disch gnd cont trig 4 8 37 6 1 5 2 thres r c c c 0.01 c c = 14.7 m f r c = 100 k w output c reset v cc out disch gnd cont trig 4 8 37 6 1 5 2 thres r b 33 k w 0.001 0.01 m f c b = 4.7 m f r b = 100 k w output b output a r a = 100 k w c a = 10 m f m f 0.01 m f 0.001 33 k w ra thres 2 5 1 6 7 3 8 4 trigcont gnd disch out v cc reset m f m f c b c a pin numbers shown are for the d, jg, p , ps, and pw packages. note a: s closes momentarily at t = 0.
na555 , NE555 , sa555 , se555 slfs022i ? september 1973 ? revised september 2014 www.ti.com typical applications (continued) 9.2.4.1 design requirements the sequential timer application chains together multiple mono-stable timers. the joining components are the 33- k resistors and 0.001- f capacitors. the output high to low edge passes a 10- s start pulse to the next monostable. 9.2.4.2 detailed design procedure the timing resistors and capacitors can be chosen using this formula. t w = 1.1 r c. 9.2.4.3 application curves figure 23. sequential timer waveforms 10 power supply recommendations the devices are designed to operate from an input voltage supply range between 4.5 v and 16 v. (18 v for se555). a bypass capacitor is highly recommended from vcc to ground pin; ceramic 0.1 f capacitor is sufficient. 18 submit documentation feedback copyright ? 1973 ? 2014, texas instruments incorporated product folder links: na555 NE555 sa555 se555 v oltage ? 5 v/div t ? t ime ? 1 s/div ????? ????? ????? see figure 22 ???? ???? ???? output a ???? ???? ???? ???? output b ???? ???? ???? output c ??? ??? ??? ??? t = 0 ????? ????? ????? t w c = 1.1 r c c c ?? ?? ?? t w c ????? ????? ????? t w b = 1.1 r b c b ????? ????? ????? t w a = 1.1 r a c a ??? ??? ??? ??? t w a ??? ??? ??? ??? t w b
na555 , NE555 , sa555 , se555 www.ti.com slfs022i ? september 1973 ? revised september 2014 11 device and documentation support 11.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 2. related links technical tools & support & parts product folder sample & buy documents software community na555 click here click here click here click here click here NE555 click here click here click here click here click here sa555 click here click here click here click here click here se555 click here click here click here click here click here 11.2 trademarks all trademarks are the property of their respective owners. 11.3 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 glossary slyz022 ? ti glossary. this glossary lists and explains terms, acronyms and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser based versions of this data sheet, refer to the left hand navigation. copyright ? 1973 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: na555 NE555 sa555 se555
package option addendum www.ti.com 26-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples jm38510/10901bpa active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 jm38510 /10901bpa m38510/10901bpa active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 jm38510 /10901bpa na555d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 na555 na555dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 na555 na555dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 na555 na555p active pdip p 8 50 green (rohs & no sb/br) cu nipdau | cu sn n / a for pkg type -40 to 105 na555p na555pe4 active pdip p 8 50 tbd call ti call ti -40 to 105 na555p NE555d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 NE555 NE555dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 NE555 NE555dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim 0 to 70 NE555 NE555dre4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 NE555 NE555drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 NE555 NE555p active pdip p 8 50 green (rohs & no sb/br) cu nipdau | cu sn n / a for pkg type 0 to 70 NE555p NE555pe4 active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type 0 to 70 NE555p NE555ps active so ps 8 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim n555 NE555psr active so ps 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555psre4 active so ps 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555
package option addendum www.ti.com 26-sep-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples NE555psrg4 active so ps 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555pw active tssop pw 8 150 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555pwg4 active tssop pw 8 150 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555pwr active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555pwre4 active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 NE555pwrg4 active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 n555 sa555d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 sa555 sa555de4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 sa555 sa555dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 sa555 sa555dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 85 sa555 sa555dre4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 sa555 sa555drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 sa555 sa555p active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 sa555p sa555pe4 active pdip p 8 50 green (rohs & no sb/br) cu nipdau n / a for pkg type -40 to 85 sa555p se555d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 se555 se555dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 se555 se555dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 se555 se555drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 se555
package option addendum www.ti.com 26-sep-2018 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples se555fkb active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 se555fkb se555jg active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 se555jg se555jgb active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 se555jgb se555p active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 se555p (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 26-sep-2018 addendum-page 4 other qualified versions of se555, se555m : ? catalog: se555 ? military: se555m ? space: se555-sp , se555-sp note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications ? space - radiation tolerant, ceramic packaging and qualified for use in space-based application
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant na555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 na555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 NE555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 NE555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 NE555dr soic d 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 q1 NE555dr soic d 8 2500 330.0 15.4 6.4 5.2 2.1 8.0 12.0 q1 NE555drg4 soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 NE555drg4 soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 NE555psr so ps 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 q1 NE555pwr tssop pw 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 q1 sa555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 sa555drg4 soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 se555dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 se555drg4 soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 22-sep-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) na555dr soic d 8 2500 340.5 338.1 20.6 na555dr soic d 8 2500 367.0 367.0 35.0 NE555dr soic d 8 2500 340.5 338.1 20.6 NE555dr soic d 8 2500 367.0 367.0 35.0 NE555dr soic d 8 2500 364.0 364.0 27.0 NE555dr soic d 8 2500 333.2 345.9 28.6 NE555drg4 soic d 8 2500 340.5 338.1 20.6 NE555drg4 soic d 8 2500 367.0 367.0 35.0 NE555psr so ps 8 2000 367.0 367.0 38.0 NE555pwr tssop pw 8 2000 367.0 367.0 35.0 sa555dr soic d 8 2500 340.5 338.1 20.6 sa555drg4 soic d 8 2500 340.5 338.1 20.6 se555dr soic d 8 2500 367.0 367.0 38.0 se555drg4 soic d 8 2500 367.0 367.0 38.0 package materials information www.ti.com 22-sep-2016 pack materials-page 2

mechanical data mcer001a january 1995 revised january 1997 post office box 655303 ? dallas, texas 75265 jg (r-gdip-t8) ceramic dual-in-line 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip1-t8

www.ti.com package outline c typ 6.6 6.2 1.2 max 6x 0.65 8x 0.30 0.19 2x 1.95 0.15 0.05 (0.15) typ 0 - 8 0.25 gage plane 0.75 0.50 a note 3 3.1 2.9 b note 4 4.5 4.3 4221848/a 02/2015 tssop - 1.2 mm max height pw0008a small outline package notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm per side. 5. reference jedec registration mo-153, variation aa. 1 8 0.1 c a b 5 4 pin 1 id area seating plane 0.1 c see detail a detail a typical scale 2.800
www.ti.com example board layout (5.8) 0.05 max all around 0.05 min all around 8x (1.5) 8x (0.45) 6x (0.65) (r ) typ 0.05 4221848/a 02/2015 tssop - 1.2 mm max height pw0008a small outline package symm symm land pattern example scale:10x 1 4 5 8 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details not to scale solder mask opening metal under solder mask solder mask defined
www.ti.com example stencil design (5.8) 6x (0.65) 8x (0.45) 8x (1.5) (r ) typ 0.05 4221848/a 02/2015 tssop - 1.2 mm max height pw0008a small outline package notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 4 5 8 solder paste example based on 0.125 mm thick stencil scale:10x
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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